1. Field of Invention
This invention relates generally to semiconductor memories and specifically to content addressable memories.
2. Description of Related Art
A CAM includes an array of memory cells arranged in a matrix of rows and columns. Each memory cell stores a single bit of digital information, i.e., either logic zero or logic one. The bits stored within a row of memory cells constitute a CAM word. During compare operations, a comparand word is received at appropriate input terminals of the CAM and then compared with all the CAM words. For each CAM word that matches the comparand word, a corresponding match line signal is asserted to indicate a match condition. When there is a match condition, the index or address of the matching CAM word is read from the CAM. Associative information stored in, for instance, an associated RAM, may also be provided.
FIG. 1 shows a typical CAM row 1 as having n CAM cells 10(1)-10(n) each coupled to an associated match line ML. A pull-up transistor 12, coupled between a supply voltage VDD and match line ML, has a gate tied to ground potential, and therefore remains in a conductive state. Prior to each compare operation between an n-bit comparand word and an n-bit CAM word stored in CAM cells 10(1)-10(n), match line ML is pre-charged to supply voltage VDD via pull-up transistor 12. The n-bits of the comparand word are compared with corresponding bits of the CAM word in respective CAM cells 10(1)-10(n). If all bits of the comparand word match corresponding bits of the CAM word, the match line ML remains charged to indicate a match condition. Conversely, if one of the comparand bits does not match the corresponding CAM bit, the CAM cell 10 storing that CAM bit discharges match line ML toward ground potential to indicate a mismatch condition.
As described above, the match lines in a CAM array are typically pre-charged to the supply voltage VDD for each and every compare operation. Thus, for each mismatch condition, an associated match line ML is first charged toward VDD and then discharged toward ground potential. Current flow associated with this charging and discharging results in undesirable power consumption. Further, as the number of CAM cells in each row of a CAM array increases, capacitive loading on the match lines increases accordingly. As loading on the match lines increases, the current required to charge the match lines toward the supply voltage increases. Accordingly, as CAM words are widened, for example, to accommodate longer Internet addresses, power consumption resulting from charging the match lines during compare operations may significantly increase. Therefore, as CAM words become wider, it is desirable to reduce power consumption during compare operations.
A method and apparatus are disclosed that may reduce power consumption in a CAM during compare operations. In accordance with one embodiment the present invention, rows of the CAM array are partitioned into a plurality of row segments, with each row segment having a corresponding match line segment. A first match line segment is pre-charged to enable detection of match conditions in the associated first row segment. Subsequent match line segments are then selectively pre-charged in response to the match conditions in the preceding row segments.
In one embodiment, rows of a CAM array are partitioned into first and second row segments. A first match line segment is pre-charged to enable detection of match conditions within the associated first row segment. If there is a match condition in the first row segment, a second match line segment is pre-charged to enable detection of match conditions in the associated second row segment. If there is also a match condition in the second row segment, a match condition is indicated for the row. A mismatch condition in the second row segment indicates a mismatch condition for the row. Conversely, if there is a mismatch condition in the first row segment, the second match line segment is not pre-charged, thereby disabling the second match line segment. In this manner, a mismatch condition may be indicated for the row without pre-charging the second match line segment. In this case, where only the first match line segment is pre-charged during the compare operation, power consumption associated with pre-charging the second match line segment is saved. Accordingly, where the first and second row segments include equal numbers of CAM cells, and thus the first and second match line segments are approximately equally loaded by the CAM cells, present embodiments may achieve power savings of up to 50% during such pre-charge operations. Since power savings is proportional to the number CAM cells per row that are enabled during each compare operation, higher power savings may be achieved by increasing the number of row segments, or by having different numbers of CAM cells in each row segment.
In other embodiments, the match line segments in first and second row segments are pre-charged to enable detection of match conditions therein. The match line segments in one or more subsequent odd row segments are selectively pre-charged in response to match conditions in the first row segment, and the match line segments in one or more subsequent even row segments are selectively pre-charged in response to match conditions in the second row segment. Thereafter, match conditions in each subsequent row segment may be used to selectively pre-charge one or more additional row segments.
In an exemplary embodiment, each row includes four row segments of CAM cells. The match line segments in the first and second row segments are pre-charged to enable detection of match conditions therein. If there is a match condition in the first row segment, the match line segment in the third row segment is pre-charged to enable detection of match conditions therein. Similarly, if there is a match condition in the second row segment, the match line segment in the fourth row segment is pre-charged to enable detection of match conditions therein. If there are also match conditions in the third and fourth second row segments, a match condition is indicated for the row. In this manner, the pre-charging of the third match line segment may be overlapped with compare operations in the second row segment so that compare operations in the third row segment may be commenced almost immediately after compare operations in the second row segment, i.e., without incurring delays associated with pre-charging the third match line segment. Similarly, the pre-charging of the fourth match line segment may be overlapped with compare operations in the third row segment so that compare operations in the fourth row segment may be commenced almost immediately after compare operations in the third row segment, i.e., without incurring delays associated with pre-charging the fourth match line segment. In this manner, compare operations for the row may be more efficiently executed to improve performance.
Conversely, if there is a mismatch condition in the first row segment, the third match line segment is not pre-charged, thereby disabling the third match line segment. If there is a mismatch condition in the second row segment, the fourth match line segment is not pre-charged, thereby disabling the fourth match line segment. In one embodiment, the fourth match line segment is not pre-charged if there is a mismatch condition in either the first or second row segments. A mismatch condition in any of the row segments causes a mismatch condition for the row. In this manner, a mismatch condition may be indicated for the row without pre-charging all match line segments, thereby reducing power consumption associated with pre-charging match line segments.